1. Field of the Invention
This invention relates to a serial to parallel conversion circuit, and more particularly to a serial to parallel conversion circuit for which high speed operation is required.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing the construction of a conventional example of a serial to parallel conversion circuit of the type mentioned, and FIGS. 2 and 3 are signal timing charts illustrating operation of the conventional example of FIG. 1.
In the present conventional example, the serial to parallel conversion circuit includes 10 high speed flip-flops of the same configuration and 10 medium speed flip-flops of the same configuration. In the following description, the former flip-flops are referred to as FF1, and the latter flip-flops are referred to as FF2. Each of flip-flops FF1 has positive phase signal input and output terminals and negative phase signal input and output terminals for inputting and outputting differential signals, respectively, and differential clock input terminals for inputting differential clocks, and performs the same logic operation as a D-type flip-flop. Each of flip-flops FF2 is also formed as a D-type flip-flop. The connection wherein the positive phase side one of differential signals is connected to the positive phase input terminal side of a flip-flop and the negative phase side one of the differential signals is connected to the negative phase input terminal side of the flip-flop is hereinafter referred to as a positive phase connection, but the other connection wherein the positive sides and the negative sides are connected in a crossing relationship is hereinafter referred to as a negative phase connection.
First flip-flop FF1 3 is connected in positive phase connection with the signal input terminals thereof connected to differential data input terminals 1 and with the clock input terminals thereof connected to differential clock input terminals 2. Second flip-flop FF1 4 is connected in negative phase connection at the differential signal output terminals and the differential signal input terminals thereof and with the clock input terminals thereof connected in positive phase connection to differential clock input terminals 2 thereby to construct a known divide-by-two circuit, which outputs two-division signals of the inputted differential clocks. Eight flip-flops FF1 from third flip-flop FF1 5 to tenth flip-flop FF1 12 are connected so that the positive phase signal output terminal of each of them is connected in a cascade connection to the positive phase signal input terminal of the flip-flop FF1 at the next stage, while the clock input terminals of all of them are connected in a positive phase connection to differential clock input terminals 2, thereby forming an 8-bit shift register. The positive phase signal input terminal of third flip-flop FF1 5 is connected to the positive phase signal output terminal of first flip-flop FF1 3. It is to be noted that, though not shown in the block diagram of FIG. 1, the negative phase signal input terminals of the eight FF1 flip-flops from third flip-flop FF1 5 to tenth flip-flop FF1 12 are connected to a reference level (the voltage midpoint between high and low logical levels). Ninth flip-flop FF2 21 and tenth flip-flop FF2 22 form a known divide-by-four circuit, and the Q signal output terminal of ninth flip-flop FF2 21 is connected to the signal input terminal of tenth flip-flop FF2 22 while the Q signal output terminal of tenth flip-flop FF2 22 is connected to the signal input terminal of ninth flip-flop FF2 21. The negative phase signal output of second flip-flop FF1 4 is input as a clock signal to the clock input terminals of ninth flip-flop FF2 21 and tenth flip-flop FF2 22, and a clock signal of a frequency obtained by dividing differential clocks input from differential clock input terminals 2 by eight is output from the Q signal output terminal of ninth flip-flop FF2 21. Twelfth to nineteenth flip-flops FF2 24 to FF2 31 are connected at the signal input terminals thereof to the positive phase signal output terminals of flip-flops FF1 5 to FF1 12 forming the stages of the shift register described above, respectively, and connected at the Q signal output terminals thereof to output terminals 39, 38, 37, 36, 35, 34, 33 and 32, respectively, in order. The divide-by-eight positive phase signal described above is connected to the clock input terminals of all flip-flops FF2 24 to FF2 31.
Operation of the present conventional example is described below with reference to the drawings.
As shown in FIG. 2, high speed 8-bit serial signals D.sub.1.sup.n D.sub.8.sup.n (n represents the input order number of data in units of 8 bits) input from differential data input terminals 1 are input to the differential signal input terminals of first flip-flop FF1 3. First flip-flop FF1 3 re-times and shapes the input signals with high speed differential clocks input from differential clock input terminals 2 and successively outputs the shaped signals from the positive phase signal output terminal thereof to the shift register at the next stage. FIG. 2 illustrates a situation wherein the bit signals are successively shifted in flip-flops FF1 3, 5 to 12 in the shift register in response to the timings of differential clocks. Second flip-flop FF1 4 outputs a negative phase two-division signal from the negative phase signal output terminal, and ninth and tenth flip-flops FF2 21 and 22 further divide the negative phase two-division signal by four to obtain divide-by-eight clocks and inputs the divide-by-eight clocks to the clock terminals of twelfth to nineteenth flip-flops FF2 24 to FF2 31. Time difference d between the negative phase signal and the divide-by-eight signal shown in FIG. 2 represents the propagation delay time of ninth medium speed flip-flop FF2 21. Accordingly, bit signals D.sub.1.sup.n D.sub.8.sup.n of a series of an 8-bit serial signal, which are the outputs of each stage of the shift register, are read out at a time from twelfth to nineteenth flip-flops FF2 24 to FF2 31 at the timing of an divide-by-eight clock output from ninth flip-flop FF2 21 and are output as an 8-bit parallel signal from output terminals 32 to 39.
In the serial to parallel conversion circuit of the conventional example described above, ten high speed flip-flops FF1 are used. When making a flip-flop circuit by a CMOS process,is attempted in order to achieve such a high speed operation as described above, flip-flops must be constructed using gates of the NMOS type. However, an NMOS type gate employs an active load, and consequently, electric current always flows through the gate. In order to achieve a higher speed operation, the value of the electric current must be increased, and consequently, the flip-flop circuit which employs the gates of the NMOS type exhibits very high power dissipation when compared with flip-flop circuits of the CMOS type. Accordingly, the serial to parallel conversion circuit of the conventional example described above is disadvantageous in that, since the power dissipation of the entire serial to parallel conversion circuit becomes excessively high, in order to form the serial to parallel conversion circuit into a single chip together with other large scale logic circuits, huge heat radiation fins or special water-cooling mounting parts are required or it is impossible to form the serial to parallel conversion circuit into a single chip.